| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Number of Pins | 20 Pin |
| Supply Voltage (DC) | 2.00V ~ 5.50V |
| Case/Package | TSSOP-20 |
| Number of Outputs | 8 Output |
| Output Current | 8 mA |
| Number of Circuits | 8 Circuit |
| Number of Positions | 20 Position |
| Number of Bits | 8 Bit |
| Propagation Delay Max (tpd) | 10.0 ns |
| Voltage Nodes | 5.00 V, 3.30 V |
| Output Current Drive | -1.00 mA |
| Number of Inputs | 8 Input |
| Operating Temperature (Max) | 85 ℃ |
| Operating Temperature (Min) | -40 ℃ |
| Supply Voltage | 2V ~ 5.5V |
| Supply Voltage (Max) | 5.5 V |
| Supply Voltage (Min) | 2 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Each |
| Operating Temperature | -40℃ ~ 85℃ |
The SN74AHC573PW is an octal transparent D-type Latch with 3-state outputs. It is designed for 2 to 5.5V VCC operation. The 3-state outputs directly drive bus lines. When the LE input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. A buffered OE input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pull-up components. OE\ does not affect the internal operations of the latches.
● Latch-up performance exceeds 250mA per JESD 17
● Green product and no Sb/Br
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