| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Number of Pins | 14 Pin |
| Supply Voltage (DC) | 4.50V ~ 5.50V |
| Case/Package | TSSOP-14 |
| Number of Outputs | 4 Output |
| Output Current | 8 mA |
| Number of Channels | 4 Channel |
| Number of Positions | 14 Position |
| Number of Bits | 4 Bit |
| Propagation Delay Max (tpd) | 8.50 ns |
| Voltage Nodes | 5.00 V |
| Output Current Drive | -1.00 mA |
| Number of Inputs | 2 Input |
| Operating Temperature (Max) | 85 ℃ |
| Operating Temperature (Min) | -40 ℃ |
| Supply Voltage | 4.5V ~ 5.5V |
| Supply Voltage (Max) | 5.5 V |
| Supply Voltage (Min) | 4.5 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Each |
| Size-Length | 5 mm |
| Size-Width | 4.4 mm |
| Size-Height | 1.15 mm |
| Operating Temperature | -40℃ ~ 85℃ |
The SN74AHCT125PW is a quadruple Bus Buffer Gate with 3-state outputs. Each output is disabled when the associated output-enable (OE)\ input is high. When OE\ is low, the respective gate passes the data from the A input to its Y output. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pull-up resistor, the minimum value of the resistor is determined by the current-sinking capability of the driver.
● Inputs are TTL-voltage compatible
● Latch-up performance exceeds 250mA per JESD 17
● ESD protection exceeds JESD 22
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