| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Frequency | 35 MHz |
| Number of Pins | 20 Pin |
| Supply Voltage (DC) | 4.50V ~ 5.50V |
| Case/Package | DIP-20 |
| Number of Outputs | 8 Output |
| Output Current | 24 mA |
| Number of Circuits | 8 Circuit |
| Number of Channels | 8 Channel |
| Number of Positions | 20 Position |
| Clock Speed | 35 MHz |
| Number of Bits | 8 Bit |
| Propagation Delay Max (tpd) | 16.0 ns |
| Polarity | Non-Inverting |
| Voltage Nodes | 5.00 V |
| Number of Gates | 8 Gate |
| Output Current Drive | -108 µA |
| Number of Inputs | 8 Input |
| Operating Temperature (Max) | 70 ℃ |
| Operating Temperature (Min) | 0 ℃ |
| Supply Voltage | 4.5V ~ 5.5V |
| Supply Voltage (Max) | 5.5 V |
| Supply Voltage (Min) | 4.5 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
| Size-Length | 24.33 mm |
| Size-Width | 6.35 mm |
| Size-Height | 4.57 mm |
| Operating Temperature | 0℃ ~ 70℃ (TA) |
The SN74ALS374AN is an octal edge triggered D-type Flip-flop with 3-state outputs. It is designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers and working registers. On the positive transition of the clock input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered OE\ input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pull-up components. OE\ does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
● Full parallel access for loading
● Buffered control inputs
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