| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Frequency | 24 MHz |
| Number of Pins | 16 Pin |
| Supply Voltage (DC) | 2.00V ~ 6.00V |
| Case/Package | DIP-16 |
| Number of Outputs | 1 Output |
| Output Current | 5.2 mA |
| Number of Circuits | 2 Circuit |
| Number of Channels | 2 Channel |
| Number of Positions | 16 Position |
| Clock Speed | 60 MHz |
| Number of Bits | 2 Bit |
| Propagation Delay Max (tpd) | 26.0 ns |
| Polarity | Non-Inverting, Inverting |
| Voltage Nodes | 6.00 V, 5.00 V, 2.00 V |
| Input Capacitance | 3 pF |
| Output Current Drive | -1.00 mA |
| Number of Inputs | 2 Input |
| Operating Temperature (Max) | 85 ℃ |
| Operating Temperature (Min) | -40 ℃ |
| Supply Voltage | 2V ~ 6V |
| Supply Voltage (Max) | 6 V |
| Supply Voltage (Min) | 2 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
| Size-Length | 19.3 mm |
| Size-Width | 6.35 mm |
| Size-Height | 4.57 mm |
| Operating Temperature | -40℃ ~ 85℃ |
The SN74HC112N is a dual negative-edge-triggered J-K Flip-flop with clear and preset. A low level at the preset (PRE\\) or clear (CLR\\) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the CLK pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. This versatile flip-flop performs as toggle flip-flop by tying J and K high.
● Outputs can drive up to 10 LSTTL loads
● 13ns Typical tpd
● ±4mA Output drive at 5V
● 1µA Maximum low input current
● 40µA Maximum low power consumption
TI
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
TI
TEXAS INSTRUMENTS SN74HC112DR Flip-Flop, Differential / Complementary, Negative Edge, 74HC112, JK, 13ns, 60MHz, 5.2mA, SOIC
TI
Flip Flop JK-Type Neg-Edge 2Element 16Pin PDIP Tube
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Flip Flop JK-Type Neg-Edge 2Element 16Pin SOIC Tube
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Flip Flop JK-Type Neg-Edge 2Element 16Pin SOIC T/R
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Flip Flop JK-Type Neg-Edge 2Element 16Pin SOIC Tube
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Flip Flop JK-Type Neg-Edge 2Element 16Pin SOIC Tube
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Flip Flop JK-Type Neg-Edge 2Element 16Pin SOIC T/R
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Flip Flop JK-Type Neg-Edge 2Element 16Pin PDIP Tube
TI
Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset 16-SOIC -40℃ to 85℃
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