These positive-edge-triggered D-type flip-flops have a direct clear (CLR)\ input. The HC175 devices feature complementary outputs from each flip-flop.
●Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output.
● Wide Operating Voltage Range of 2 V to 6 V
● Outputs Can Drive Up To 10 LSTTL Loads
● Low Power Consumption, 80-µA Max ICC
● Contain Four Flip-Flops With Double-Rail Outputs
● Typical tpd = 13 ns
● ±4-mA Output Drive at 5 V
● Low Input Current of 1 µA Max
● Applications Include:
● Buffer/Storage Registers
● Shift Registers
● Pattern Generators
