| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Frequency | 60 MHz |
| Number of Pins | 16 Pin |
| Digital Logic Level | CMOS |
| Supply Voltage (DC) | 2.00V ~ 6.00V |
| Case/Package | DIP-16 |
| Number of Outputs | 4 Output |
| Output Current | 5.2 mA |
| Number of Circuits | 4 Circuit |
| Number of Channels | 4 Channel |
| Number of Positions | 16 Position |
| Clock Speed | 60 MHz |
| Number of Bits | 4 Bit |
| Propagation Delay Max (tpd) | 32.0 ns |
| Polarity | Non-Inverting, Inverting |
| Voltage Nodes | 6.00 V, 5.00 V, 2.00 V |
| Input Capacitance | 3 pF |
| Output Current Drive | -1.00 mA |
| Number of Inputs | 4 Input |
| Operating Temperature (Max) | 85 ℃ |
| Operating Temperature (Min) | -40 ℃ |
| Supply Voltage | 2V ~ 6V |
| Supply Voltage (Max) | 6 V |
| Supply Voltage (Min) | 2 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
| Size-Length | 19.3 mm |
| Size-Width | 6.35 mm |
| Size-Height | 4.57 mm |
| Operating Temperature | -40℃ ~ 85℃ |
The SN74HC175N is a quadruple D-type Flip-flop with clear. It has a direct clear (CLR\\) input. It features complementary outputs from each flip-flop. Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of clock. When clock is at either the high or low level, the D input has no effect at the output.
● Outputs can drive up to 10 LSTTL loads
● Contain four flip-flops with double-rail outputs
● 80µA Maximum low power consumption
● 13ns Typical tpd
● ±4mA Output drive at 5V
● 1µA Maximum low input current
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TEXAS INSTRUMENTS SN74HC175PWR Flip-Flop, Complementary, Differential, Positive Edge, 74HC175, D, 13ns, 29MHz, 5.2mA, TSSOP
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TEXAS INSTRUMENTS SN74HC175D Flip-Flop, Complementary Output, Positive Edge, 74HC175, D, 13ns, 29MHz, 5.2mA, SOIC
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