| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Frequency | 37 MHz |
| Number of Pins | 20 Pin |
| Digital Logic Level | TTL |
| Supply Voltage (DC) | 4.50V ~ 5.50V |
| Case/Package | DIP-20 |
| Number of Outputs | 8 Output |
| Output Current | 4 mA |
| Number of Circuits | 8 Circuit |
| Number of Channels | 8 Channel |
| Number of Positions | 20 Position |
| Clock Speed | 37 MHz |
| Number of Bits | 8 Bit |
| Propagation Delay Max (tpd) | 36.0 ns |
| Polarity | Non-Inverting |
| Voltage Nodes | 5.00 V |
| Input Capacitance | 3 pF |
| Output Current Drive | -1.00 mA |
| Number of Inputs | 8 Input |
| Operating Temperature (Max) | 85 ℃ |
| Operating Temperature (Min) | -40 ℃ |
| Supply Voltage | 4.5V ~ 5.5V |
| Supply Voltage (Max) | 5.5 V |
| Supply Voltage (Min) | 4.5 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
| Size-Length | 24.33 mm |
| Size-Width | 6.35 mm |
| Size-Height | 4.57 mm |
| Operating Temperature | -40℃ ~ 85℃ |
The SN74HCT273N is an octal positive-edge-triggered D-type Flip-flop with clear and common enable input. The HCT273 devices are similar to the HCT377 devices, but feature a common clear enable (CLR\\) input instead of a latched clock. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. The circuits are designed to prevent false clocking by transitions at (CLR\\).
● Outputs can drive up to 10 LSTTL loads
● Inputs are TTL-voltage compatible
● Typical tpd = 12ns
● 80µA Maximum low power consumption
● ±4mA Output drive at 5V
● 1µA Maximum low input current
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TEXAS INSTRUMENTS SN74HCT273N Flip-Flop, with Clear, Non Inverted, Positive Edge, 74HCT273, D, 12ns, 37MHz, 4mA, DIP
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