The SN54/74LS280 is a Universal 9-Bit Parity Generator/Checker. It features odd/even outputs to facilitate either odd or even parity. By cascading, the word length is easily expanded. The LS280 is designed without the expander input implementation, but the corresponding function is provided by an input at Pin 4 and the absence of any connection at Pin 3. This design permits the LS280 to be substituted for the LS180 which results in improved performance. The LS280 has buffered inputs to lower the drive requirements to one LS unit load.
●• Generates Either Odd or Even Parity for Nine Data Lines
●• Typical Data-to-Output Delay of only 33 ns
●• Cascadable for n-Bits
●• Can Be Used To Upgrade Systems Using MSI Parity Circuits
●• Typical Power Dissipation = 80 mW
Freescale
4 Pages / 0.14 MByte
TI
Buffer/Line Driver 1CH Non-Inverting 3-ST CMOS 5Pin SC-70 T/R
TI
Buffer/Line Driver 1CH Non-Inverting 3-ST CMOS 5Pin SOT-23 T/R
TI
Shift Register, HC Family, 74HC164, Serial to Parallel, 1Element, 8Bit, DIP, 14Pins
TI
Inverter, Schmitt Trigger, 74LVC1G14, 1Input, 32mA, 1.65V to 5.5V, SOT-23-5
TI
Inverter Schmitt Trigger 6Element CMOS 14Pin TSSOP Inverter Schmitt Trigger 6Element CMOS 14Pin TSSOP
TI
Buffer/Line Driver 8CH Non-Inverting 3-ST CMOS 20Pin TSSOP T/R
TI
Inverter, Schmitt Trigger, 74AHC1G14, 1Input, 8mA, 2V to 5.5V, SOT-23-5
TI
TEXAS INSTRUMENTS SN74LVC4245APWR Transceiver, Non-Inverting, 2.7V to 3.6V, 4.5V to 5.5V, TSSOP-24
TI
OR Gate 1Element 2IN CMOS 5Pin SOT-23 T/R
TI
Flip-Flop, Differential / Complementary, Positive Edge, 74LVC74, D, 4.1ns, 200MHz, 32mA, VSSOP
Part Datasheet PDF Search
72,405,303 Parts Datasheet PDF, Update more than 5,000 PDF files ervery day.
