The SN54290/SN74290, SN54LS290/SN74LS290, SN54293/SN74293, and SN54LS293/SN74LS293 counters are electrically and functionally identical to the SN5490A/SN7490A, SN54LS90/SN74LS90, SN5493A/SN7493A, and SN54LS93/SN74LS93, respectively. Only the arrangement of the terminals has been changed for the "290, "LS290, "293, and "LS293.
●Each of these monolithic counters contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and a three-stage binary counter for which the count cycle length is divide-by-five for the "290 and "LS290 and divide-by-eight for the "293 and "LS293.
●All of these counters have a gated zero reset and the "290 and "LS290 also have gated set-to-nine inputs for use in BCD nine"s complement applications.
●To use the maximum count length (decade or four-bit binary) of these counters, the B input is connected to the QA output. The input count pulses are applied to input A and the outputs are as described in the appropriate function table. A symmetrical divide-by-ten count can be obtained from the "290 and "LS290 counters by connecting the QD output to the A input and applying the input count to the B input which gives a divide-by-ten square wave at output QA.
●"290, "LS290...DECADE COUNTERS
●"293, "LS293...4–BIT BINARY COUNTERS
● GND and VCC on Corner Pins (Pins 7 and 14 Respectively)
