| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Number of Pins | 5 Pin |
| Supply Voltage (DC) | 1.65V ~ 5.50V |
| Case/Package | SOT-23-5 |
| Number of Outputs | 1 Output |
| Output Current | 32 mA |
| Number of Circuits | 1 Circuit |
| Number of Positions | 5 Position |
| Number of Bits | 1 Bit |
| Propagation Delay Max (tpd) | 4.40 ns |
| Voltage Nodes | 5.00 V, 3.30 V, 2.50 V, 1.80 V |
| Number of Gates | 1 Gate |
| Output Current Drive | -1.00 mA |
| Number of Inputs | 2 Input |
| Operating Temperature (Max) | 125 ℃ |
| Operating Temperature (Min) | -40 ℃ |
| Supply Voltage | 1.65V ~ 5.5V |
| Supply Voltage (Max) | 5.5 V |
| Supply Voltage (Min) | 1.65 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tape & Reel (TR) |
| Size-Length | 2.9 mm |
| Size-Width | 1.6 mm |
| Size-Height | 1.15 mm |
| Operating Temperature | -40℃ ~ 85℃ |
The SN74LVC1G132DBVT is a single 2-input NAND Gate with Schmitt-trigger input. The device with different input threshold levels for positive-going (VT+) and negative-going (VT-) signals. This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals. This device is fully specified for partial-power-down applications using IOFF. The IOFF circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
● 5.3ns at 3.3V Maximum TPD
● Low power consumption
● IOFF supports partial-power-down mode operation
● Latch-up performance exceeds 100mA per JESD 78
● ESD protection exceeds JESD 22
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