The TMS320C44 DSP is a 32-bit, floating-point processor manufactured in 0.72-µm double-level-metal CMOS technology. The TMS320C44 is part of the TMS320C4x generation of DSPs from Texas Instruments. The on-chip parallel-processing capabilities of the C44 make the immense floating-point performance required by many applications achievable.
● Highest Performance Floating-Point Digital Signal Processor (DSP)
● TMS320C44-60:
●33-ns Instruction Cycle Time,
●330 MOPS, 60 MFLOPS,
●30 MIPS, 336M Bytes/s
● TMS320C44-50:
●40-ns Instruction Cycle Time
● Four Communication Ports
● Six-Channel Direct Memory Address (DMA) Coprocessor
● Single-Cycle Conversion to and From IEEE-754 Floating-Point Format
● Single Cycle, 1/x, 1/x
● Source-Code Compatible With "C3x and "C4x
● Single-Cycle 40-Bit Floating-Point, 32-Bit Integer Multipliers
● Twelve 40-Bit Registers, Eight Auxiliary Registers, 14 Control Registers, and Two Timers
● IEEE-1149.1 (JTAG) Boundary-Scan Compatible
● Two Identical External Data and Address Buses Supporting Shared Memory Systems and High Data-Rate, Single-Cycle Transfers
● High Port-Data rate of 120M Bytes/s (TMS320C44-60)(Each Bus)
● 128M-Byte Program/Data/Peripheral Address Space
● Memory-Access Request for Fast, Intelligent Bus Arbitration
● Separate Address-Bus, Data-Bus, and Control-Enable Pins
● Four Sets of Memory-Control Signals Support Different Speed Memories in Hardware
● Fabricated using 0.72-µm Enhanced Performance Implanted CMOS (EPIC) Technology by Texas Instruments (TI)
● Separate Internal Program-, Data-, and DMA-Coprocessor Buses for Support of Massive Concurrent I/O of Program and Data, Thereby Maximizing Sustained CPU Performance
● IDLE2 Clock-Stop Power-Down Mode
● Communication-Port-Direction Pin
● On-Chip Program Cache and Dual-Access/Single-Cycle RAM for Increased Memory-Access Performance
● 512-Byte Instruction Cache
● 8K Bytes of Single-Cycle Dual-Access Program or Data RAM
● ROM-Based Boot Loader Supports Program Bootup Using 8-, 16-, or 32-Bit Memories or One of the Communication Ports
● Software-Communication-Port Reset
● NMI\ With Bus-Grant Feature
● 304-Pin Plastic Quad flatpack (PDB Suffix)
●IEEE standard 1149.1 - 1990 Standard Test-Access Port and Boundary-Scan Architecture
●EPIC and TI are trademarks of Texas Instruments Incorporated.
●All trademarks are the property of their respective owners.
