● High-Performance Fixed-Point Digital Signal Processor (DSP) — TMS320C6204
● 5-ns Instruction Cycle Time
● 200-MHz Clock Rate
● Eight 32-Bit Instructions/Cycle
● 1600 MIPS
● C6204 GLW Ball Grid Array (BGA) Package is Pin-Compatible With the C6202/02B/03 GLS BGA Package
● VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C62x™ DSP Core
● Eight Highly Independent Functional Units:
● Six ALUs (32-/40-Bit)
● Two 16-Bit Multipliers (32-Bit Result)
● Load-Store Architecture With 32 32-Bit General-Purpose Registers
● Instruction Packing Reduces Code Size
● All Instructions Conditional
● Instruction Set Features
● Byte-Addressable (8-, 16-, 32-Bit Data)
● 8-Bit Overflow Protection
● Saturation
● Bit-Field Extract, Set, Clear
● Bit-Counting
● Normalization
● 1M-Bit On-Chip SRAM
● 512K-Bit Internal Program/Cache (16K 32-Bit Instructions)
● 512K-Bit Dual-Access Internal Data (64K Bytes)
● Organized as Two 32K-Byte Blocks for Improved Concurrency
● 32-Bit External Memory Interface (EMIF)
● Glueless Interface to Synchronous Memories: SDRAM or SBSRAM
● Glueless Interface to Asynchronous Memories: SRAM and EPROM
● 52M-Byte Addressable External Memory Space
● Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel
● 32-Bit Expansion Bus (XB)
● Glueless/Low-Glue Interface to Popular PCI Bridge Chips
● Glueless/Low-Glue Interface to Popular Synchronous or Asynchronous Microprocessor Buses
● Master/Slave Functionality
● Glueless Interface to Synchronous FIFOs and Asynchronous Peripherals
● Two Multichannel Buffered Serial Ports (McBSPs)
● Direct Interface to T1/E1, MVIP, SCSA Framers
● ST-Bus-Switching Compatible
● Up to 256 Channels Each
● AC97-Compatible
● Serial-Peripheral Interface (SPI) Compatible (Motorola™)
● Two 32-Bit General-Purpose Timers
● Flexible Phase-Locked-Loop (PLL) Clock Generator
● IEEE-1149.1 (JTAG Boundary-Scan-Compatible
● 288-Pin MicroStar BGA™ Package (GHK)
● 340-Pin BGA Package (GLW)
● 0.15-µm/5-Level Metal Process
● CMOS Technology
● 3.3-V I/Os, 1.5-V Internal
