TMS320C6204 Datasheet PDF - TI

The TMS320C62x™ DSPs (including the TMS320C6204 device) compose the fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C6204 (C6204) device is based on the high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making the C6204 an excellent choice for multichannel and multifunction applications.

●With performance of up to 1600 million instructions per second (MIPS) at a clock rate of 200 MHz, the C6204 offers cost-effective solutions to high-performance DSP-programming challenges. The C6204 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6204 can produce two multiply-accumulates (MACs) per cycle for a total of 400 million MACs per second (MMACS). The C6204 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

●The C6204 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped as program space. Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a 32-bit expansion bus (XB) that offers ease of interface to synchronous or asynchronous industry-standard host bus protocols, and a glueless 32-bit external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.

●The C6204 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

● High-Performance Fixed-Point Digital Signal Processor (DSP) — TMS320C6204

● 5-ns Instruction Cycle Time

● 200-MHz Clock Rate

● Eight 32-Bit Instructions/Cycle

● 1600 MIPS

● C6204 GLW Ball Grid Array (BGA) Package is Pin-Compatible With the C6202/02B/03 GLS BGA Package

● VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C62x™ DSP Core

● Eight Highly Independent Functional Units:

● Six ALUs (32-/40-Bit)

● Two 16-Bit Multipliers (32-Bit Result)

● Load-Store Architecture With 32 32-Bit General-Purpose Registers

● Instruction Packing Reduces Code Size

● All Instructions Conditional

● Instruction Set Features

● Byte-Addressable (8-, 16-, 32-Bit Data)

● 8-Bit Overflow Protection

● Saturation

● Bit-Field Extract, Set, Clear

● Bit-Counting

● Normalization

● 1M-Bit On-Chip SRAM

● 512K-Bit Internal Program/Cache (16K 32-Bit Instructions)

● 512K-Bit Dual-Access Internal Data (64K Bytes)

● Organized as Two 32K-Byte Blocks for Improved Concurrency

● 32-Bit External Memory Interface (EMIF)

● Glueless Interface to Synchronous Memories: SDRAM or SBSRAM

● Glueless Interface to Asynchronous Memories: SRAM and EPROM

● 52M-Byte Addressable External Memory Space

● Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel

● 32-Bit Expansion Bus (XB)

● Glueless/Low-Glue Interface to Popular PCI Bridge Chips

● Glueless/Low-Glue Interface to Popular Synchronous or Asynchronous Microprocessor Buses

● Master/Slave Functionality

● Glueless Interface to Synchronous FIFOs and Asynchronous Peripherals

● Two Multichannel Buffered Serial Ports (McBSPs)

● Direct Interface to T1/E1, MVIP, SCSA Framers

● ST-Bus-Switching Compatible

● Up to 256 Channels Each

● AC97-Compatible

● Serial-Peripheral Interface (SPI) Compatible (Motorola™)

● Two 32-Bit General-Purpose Timers

● Flexible Phase-Locked-Loop (PLL) Clock Generator

● IEEE-1149.1 (JTAG ) Boundary-Scan-Compatible

● 288-Pin MicroStar BGA™ Package (GHK)

● 340-Pin BGA Package (GLW)

● 0.15-µm/5-Level Metal Process

● CMOS Technology

● 3.3-V I/Os, 1.5-V Internal

●VelociTI, TMS320C62x, and MicroStar BGA are trademarks of Texas Instruments.

●Motorola is a trademark of Motorola, Inc.

●For more details, see the GLW BGA package bottom view.

●IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

●TMS320C6000, C62x, and C6000 are trademarks of Texas Instruments.

●Windows is a registered trademark of Microsoft Corporation.