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CD54HCT373, CD74HCT373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS453B – FEBRUARY 2001 – REVISED MAY 2003
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D
4.5-V to 5.5-V V
CC
Operation
D
Wide Operating Temperature Range of
–55°C to 125°C
D
Balanced Propagation Delays and
Transition Times
D
Standard Outputs Drive Up To 10 LS-TTL
Loads
D
Significant Power Reduction Compared to
LS-TTL Logic ICs
D
Inputs Are TTL-Voltage Compatible
description/ordering information
The ’HCT373 devices are octal transparent
D-type latches. When the latch-enable (LE) input
is high, the Q outputs follow the data (D) inputs.
When LE is low, the Q outputs are latched at the
logic levels of the D inputs.
A buffered output-enable (OE
) input can be used to place the eight outputs in either a normal logic state (high
or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
OE
does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE
should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
T
A
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – E Tube CD74HCT373E CD74HCT373E
55
°
Cto125
°
C
SOIC M
Tube CD74HCT373M
HCT373M
55°C
to
125°C
SOIC
M
Tape and reel CD74HCT373M96
HCT373M
CDIP – F Tube CD54HCT373F3A CD54HCT373F3A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
CD54HCT373 ...F PACKAGE
CD74HCT373 ...E OR M PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

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