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SN54AHCT125, SN74AHCT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS264D – DECEMBER 1995 – REVISED NOVEMBER 1996
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D
Inputs Are TTL-Voltage Compatible
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
High Latch-Up Immunity Exceeds 250 mA
Per JEDEC Standard JESD-17
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
Ceramic Flat (W) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
The ’AHCT125 are quadruple bus buffer gates
featuring independent line drivers with 3-state
outputs. Each output is disabled when the
associated output-enable (OE
) input is high.
When OE
is low, the respective gate passes the
data from the A input to its Y output.
The SN54AHCT125 is characterized for
operation over the full military temperature range
of –55°C to 125°C. The SN74AHCT125 is
characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
OE A
OUTPUT
Y
L H H
L LL
HXZ
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OE
1A
1Y
2OE
2A
2Y
GND
V
CC
4OE
4A
4Y
3OE
3A
3Y
SN54AHCT125 ...J OR W PACKAGE
SN74AHCT125 . . . D, DB, N, OR PW PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3OE
1Y
NC
2OE
NC
2A
1A
1OE
NC
3Y
3A
V
4OE
2Y
GND
NC
SN54AHCT125 . . . FK PACKAGE
(TOP VIEW)
CC
NC – No internal connection
ADVANCE INFORMATION concerns new products in the sampling or
preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
Copyright 1996, Texas Instruments Incorporated
EPIC is a trademark of Texas Instruments Incorporated.
ADVANCE INFORMATION

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