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TRF7960
TRF7961
SLOU186F–AUGUST 2006–REVISED AUGUST 2010
www.ti.com
5.5 Reader Communication Interface
5.5.1 Introduction
The communication interface to the reader can be configured in two ways: a parallel 8-pin interface and a
Data_Clk or a serial peripheral interface (SPI).
These modes are mutually exclusive; only one mode can be used at a time in the application.
When the SPI interface is selected, the unused I/O_2, I/O_1, and I/O_0 pins must be hard-wired according
to Table 5-30. At power up, the reader samples the status of these three pins. If they are not the same (all
High or all Low) it enters one of the possible SPI modes.
The reader always behaves as the slave while the microcontroller (MCU) behaves as the master device.
The MCU initiates all communications with the reader and is also used to communicate with the higher
levels (application layer). The reader has an IRQ pin to prompt the MCU for attention if the reader detects
a response from the proximity/vicinity integrated circuit card (PICC/VICC).
Communication is initialized by a start condition, which is expected to be followed by an
Address/Command word (Adr/Cmd). The Adr/Cmd word is 8 bits long, and its format is shown in
Table 5-31.
Table 5-30. Pin Assignment in Parallel and Serial Interface Connection or Direct Mode
Pin Parallel Parallel-Direct SPI with SS SPI without SS
DATA_ DATA_CLK DATA_CLK DATA_CLK from master DATA_CLK from master
CLK
I/O_7 A/D[7] MOSI
(1)
= data-in (reader-in) MOSI
(1)
= data-in
(reader-in)
I/O_6 A/D[6] Direct mode, data out (sub-carrier or bit stream) MISO
(2)
= data-out (MCU-out) MISO
(2)
= data-out
(MCU-out)
I/O_5
(3)
A/D[5] Direct mode, strobe – bit clock out See Note 3 See Note 3
I/O_4 A/D[4] SS – slave select
(4)
—
I/O_3 A/D[3] — — —
I/O_2 A/D[2] — at VDD at VDD
I/O_1 A/D[1] — at VDD at VSS
I/O_0 A/D[0] — at VSS at VSS
IRQ IRQ interrupt IRQ interrupt IRQ interrupt IRQ interrupt
(1) MOSI – master out, slave in
(2) MISO – master in, slave out
(3) IO_5 pin is used only for information when data is put out of the chip (for example, reading 1 byte from the chip). It is necessary first to
write in the address of the register (8 clocks) and then to generate another 8 clocks for reading out the data. The IO_5 pin goes high in
this second 8 clocks. But for normal SPI operation this pin IO_5 is not used.
(4) Slave-select pin active-low
Table 5-31. Address/Command Word Bit Distribution
Bit Description Bit Function Address Command
Bit 7 Command control bit 0 = address, 1 = command 0 1
Bit 6 Read/Write 1 = read, 0 = write R/W 0
Bit 5 Continuous address mode 1 = Cont. mode R/W 0
Bit 4 Address/Command bit 4 Adr 4 Cmd 4
Bit 3 Address/Command bit 3 Adr 3 Cmd 3
Bit 2 Address/Command bit 2 Adr 2 Cmd 2
Bit 1 Address/Command bit 1 Adr 1 Cmd 1
Bit 0 Address/Command bit 0 Adr 0 Cmd 0
36 System Description Copyright © 2006–2010, Texas Instruments Incorporated
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