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AD9522 Datasheet PDF

Part Series:AD9522 Series
Category:Clock & Timing
Description:Clock Generator -40℃ to 85℃ 64Pin LFCSP EP Tray
Document:AD9522-4BCPZ-REEL7 Datasheet PDF (86 Pages)

AD9522 Datasheet PDF Clock & Timing

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ANALOG DEVICES AD9522-5/PCBZ 12/24Channel CLOCK GEN 2 0GH

AD9522-4BCPZ - ADI Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Frequency
1.6 GHz
Number of Pins
64 Pin
Supply Voltage (DC)
3.13V (min)
Case/Package
LFCSP-64
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AD9522-4BCPZ - ADI Function Overview

Product Details
The AD9522-41 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 1.4 GHz to 1.8 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz can also be used.
The AD9522 serial interface supports both SPI and I2C® ports. An in-package EEPROM can be programmed through the serial interface and store user-defined register settings for power-up and chip reset.
The AD9522 features 12 LVDS outputs in four groups. Any of the 800 MHz LVDS outputs can be reconfigured as two 250 MHz CMOS outputs.
Each group of outputs has a divider that allows both the divide ratio (from 1 to 32) and the phase (coarse delay) to be set.
The AD9522 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. The external VCO can have an operating voltage up to 5.5 V.
The AD9522 is specified for operation over the standard industrial range of −40°C to +85°C.
The AD9520-4 is an equivalent part to the AD9522-4 featuring LVPECL / CMOS drivers instead of LVDS / CMOS drivers.
1The AD9522 is used throughout this data sheet to refer to all the members of the AD9522 family. However, when AD9522-4 is used, it is referring to that specific member of the AD9522 family.
Applications
Low jitter, low phase noise clock distribution
Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation
Broadband infrastructures
Data Sheet, Rev. 0, 10/08
### Features and Benefits
Low phase noise, phase-locked loop (PLL)
On-chip VCO tunes from 1.4 GHz to 1.8 GHz
Supports external 3.3 V/5 V VCO/VCXO to 2.4 GHz
1 differential or 2 single-ended reference inputs
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Accepts CMOS, LVPECL, or LVDS references to 250 MHz
Accepts 16.62 MHz to 33.3 MHz crystal for reference input
Optional reference clock doubler
See Data Sheet for Additional Information
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