| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Number of Pins | 24 Pin |
| Digital Logic Level | CMOS |
| Supply Voltage (DC) | 15.0 V, 18.0 V (max) |
| Case/Package | DIP-24 |
| Output Current | 6.8 mA |
| Number of Circuits | 2 Circuit |
| Number of Channels | 2 Channel |
| Number of Positions | 24 Position |
| Number of Bits | 4 Bit |
| Polarity | Non-Inverting |
| Voltage Nodes | 5.00 V, 10.0 V, 15.0 V |
| Quiescent Current | 40.0 nA |
| Operating Temperature (Max) | 125 ℃ |
| Operating Temperature (Min) | -55 ℃ |
| Supply Voltage | 3V ~ 18V |
| Supply Voltage (Max) | 18 V |
| Supply Voltage (Min) | 3 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
| Size-Height | 4.57 mm |
| Operating Temperature | -55℃ ~ 125℃ |
The CD4508BE is a dual 4-bit Latch contains two identical 4-bit latches with separate STROBE, RESET and OD control. With the STROBE line in the high state, the data on the "D" inputs appear at the corresponding "Q" outputs provided the DISABLE line is in the low state. Changing the STROBE line to the low state locks the data into the latch. A high on the RESET line forces the outputs to a low level regardless of the state of the STROBE input. The outputs are forced to the high-impedance state for bus line applications by a high level on the DISABLE input.
● Individual master reset for each 4-bit latch
● 3-state outputs with high-impedance state for bus line applications
● 100% Tested for quiescent current at 20V
● Standardized, symmetrical output characteristics
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