| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Number of Pins | 20 Pin |
| Supply Voltage (DC) | 4.50V ~ 5.50V |
| Case/Package | DIP-20 |
| Number of Outputs | 8 Output |
| Output Current | 6 mA |
| Number of Circuits | 8 Circuit |
| Number of Positions | 20 Position |
| Number of Bits | 8 Bit |
| Polarity | Non-Inverting |
| Voltage Nodes | 5.00 V |
| Number of Gates | 8 Gate |
| Number of Inputs | 8 Input |
| Operating Temperature (Max) | 125 ℃ |
| Operating Temperature (Min) | -55 ℃ |
| Supply Voltage | 4.5V ~ 5.5V |
| Supply Voltage (Max) | 5.5 V |
| Supply Voltage (Min) | 4.5 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
| Size-Length | 24.33 mm |
| Size-Width | 6.35 mm |
| Size-Height | 4.57 mm |
| Operating Temperature | -55℃ ~ 125℃ |
The CD74HCT573E is an octal CMOS Transparent D Latch with 3-state outputs. When the LE input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. A buffered OE\ input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pull-up components. OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pull-up resistor, the minimum value of the resistor is determined by the current-sinking capability of the driver.
● Balanced propagation delays and transition times
● Standard outputs drive up to 10 LS-TTL loads
● Significant power reduction compared to LS-TTL logic ICs
● Inputs are TTL-voltage compatible
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