TYPE | DESCRIPTION |
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Case/Package | DIP |
TYPE | DESCRIPTION |
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Product Lifecycle Status | Obsolete |
The SN54 /74LS112A dual JKflip-flop features individual J, K, clock, and asynchronousset and clear inputs to each flip-flop. When the clock goes HIGH,the inputs are enabled and data will be accepted. The logic level of the Jand K inputs may be allowed to change when the clock pulse is HIGH and thebistable will perform according to the truth table as long as minimum set-up andhold time are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse.
Motorola
4 Pages / 0.14 MByte
TI
Flip Flop JK-Type Neg-Edge 2Element 16Pin PDIP Tube Flip Flop JK-Type Neg-Edge 2Element 16Pin PDIP Tube
TI
Flip Flop JK-Type Neg-Edge 2Element 16Pin SOIC Tube
TI
Flip Flop JK-Type Neg-Edge 2Element 16Pin SOIC T/R
TI
Flip Flop JK-Type Neg-Edge 2Element 16Pin SOP T/R
TI
Flip Flop JK-Type Neg-Edge 2Element 16Pin SOIC T/R
Motorola
Dual JK negative edge-triggered flip-flop
TI
Flip Flop JK-Type Neg-Edge 2Element 16Pin SOP Tube
TI
IC JK TYPE NEG TRG DUAL 16DIP
TI
Flip Flop JK-Type Neg-Edge 2Element 16Pin PDIP
TI
IC JK TYPE NEG TRG DUAL 16SOIC
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