| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Frequency | 30 MHz |
| Number of Pins | 14 Pin |
| Supply Voltage (DC) | 4.75V ~ 5.25V |
| Case/Package | DIP-14 |
| Number of Outputs | 1 Output |
| Output Current | 8 mA |
| Number of Circuits | 2 Circuit |
| Number of Channels | 2 Channel |
| Number of Positions | 14 Position |
| Clock Speed | 45 MHz |
| Number of Bits | 2 Bit |
| Propagation Delay Max (tpd) | 20.0 ns |
| Voltage Nodes | 5.00 V |
| Output Current Drive | -50.0 µA |
| Number of Inputs | 2 Input |
| Operating Temperature (Max) | 70 ℃ |
| Operating Temperature (Min) | 0 ℃ |
| Supply Voltage | 4.75V ~ 5.25V |
| Supply Voltage (Max) | 5.25 V |
| Supply Voltage (Min) | 4.75 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
| Size-Length | 19.3 mm |
| Size-Width | 6.35 mm |
| Size-Height | 4.57 mm |
| Operating Temperature | 0℃ ~ 70℃ |
The SN74LS73AN is a dual J-K Flip-flop with clear with LS technology and two independent J-K flip-flops with individual J-K, clock and direct clear inputs. The LS73A contains two independent negative-edge-triggered flip-flops. The J and K inputs must be stable one setup time prior to the high-to-low clock transition for predictable operation. When the clear is low, it overrides the clock and data inputs forcing the Q output low and the Q\ output high.
● TTL input and output
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