The SN74LV125APW is a quadruple Bus Buffer Gate with 3-state outputs and designed for 2 to 5.5V VCC operation. This device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable input is high. To ensure the high-impedance state during power up or power down, tie OE to VCC through a pull-up resistor and the minimum value of the resistor is determined by the current-sinking capability of the driver.
● Support mixed-mode voltage operation on all ports
● IOFF Supports partial-power-down mode operation
● Latch-up performance exceeds 100mA per JESD 78, class II
● >2.3V at VCC = 3.3V, TA = 25°C VOHV (Output VOH undershoot)
● <0.8V at VCC = 3.3V, TA = 25°C VOLP (Output ground bounce)
● 6ns at 5V Propagation delay (tpd)
● Green product and no Sb/Br
