| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Frequency | 160 MHz |
| Number of Pins | 20 Pin |
| Supply Voltage (DC) | 2.70V ~ 5.50V |
| Case/Package | TSSOP-20 |
| Number of Outputs | 8 Output |
| Output Current | 25 mA |
| Number of Circuits | 8 Circuit |
| Number of Positions | 20 Position |
| Clock Speed | 160 MHz |
| Number of Bits | 8 Bit |
| Propagation Delay Max (tpd) | 12.5 ns |
| Polarity | Non-Inverting |
| Voltage Nodes | 5.00 V, 3.30 V, 2.50 V |
| Input Capacitance | 2 pF |
| Output Current Drive | -1.00 mA |
| Number of Inputs | 8 Input |
| Operating Temperature (Max) | 85 ℃ |
| Operating Temperature (Min) | -40 ℃ |
| Supply Voltage | 2V ~ 5.5V |
| Supply Voltage (Max) | 5.5 V |
| Supply Voltage (Min) | 2 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tape & Reel (TR) |
| Size-Length | 6.5 mm |
| Size-Width | 4.4 mm |
| Size-Height | 1.15 mm |
| Operating Temperature | -40℃ ~ 85℃ |
The SN74LV273APWR is an octal positive-edge-triggered D-type Flip-flop with clear. It is designed for 2 to 5.5V VCC operation. It supports mixed-mode voltage operation on all ports. This device is a positive-edge-triggered flip-flop with direct clear (CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D-input signal has no effect at the output.
● Latch-up performance exceeds 250mA per JESD 17
● Maximum tpd of 10.5ns at 5V
● Allows down-voltage translation
● Slow edges reduce noise
● Supports mixed-mode voltage operation on all ports
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TEXAS INSTRUMENTS SN74LV273APW Flip-Flop, with Clear, Non Inverted, Positive Edge, 74LV273, D, 6.2ns, 160MHz, 12mA, TSSOP
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