| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Frequency | 110 MHz |
| Number of Pins | 14 Pin |
| Digital Logic Level | CMOS |
| Supply Voltage (DC) | 5.00 V, 5.50 V (max) |
| Case/Package | SOIC-14 |
| Number of Outputs | 1 Output |
| Output Current | 24 mA |
| Number of Circuits | 2 Circuit |
| Number of Channels | 2 Channel |
| Number of Positions | 14 Position |
| Clock Speed | 110 MHz |
| Number of Bits | 2 Bit |
| Polarity | Non-Inverting, Inverting |
| Number of Gates | 2 Gate |
| Input Capacitance | 10 pF |
| Number of Inputs | 1 Input |
| Operating Temperature (Max) | 125 ℃ |
| Operating Temperature (Min) | -55 ℃ |
| Supply Voltage | 1.5V ~ 5.5V |
| Supply Voltage (Max) | 5.5 V |
| Supply Voltage (Min) | 1.5 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
| Size-Length | 8.65 mm |
| Size-Width | 3.91 mm |
| Size-Height | 1.58 mm |
| Operating Temperature | -55℃ ~ 125℃ |
The CD74AC74M is a dual positive-edge-triggered D-type Flip-flop with set and reset. A low level at the preset (PRE\\) or clear (CLR\\) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
● Speed of Bipolar F, AS and S, with significantly reduced power consumption
● Balanced propagation delays
● ±24mA Output drive current
● SCR-Latchup-resistant CMOS process and circuit design
● Green product and no Sb/Br
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