| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Number of Pins | 6 Pin |
| Case/Package | SC-70-6 |
| Number of Channels | 2 Channel |
| Number of Positions | 6 Position |
| Drain to Source Resistance (on) (Rds) | 0.25 Ω |
| Polarity | Dual N-Channel |
| Power Dissipation | 360 mW |
| Threshold Voltage | 1 V |
| Drain to Source Voltage (Vds) | 30 V |
| Breakdown Voltage (Drain to Source) | 30 V |
| Continuous Drain Current (Ids) | 750 mA |
| Rise Time | 1 ns |
| Input Capacitance (Ciss) | 120pF @10V(Vds) |
| Input Power (Max) | 300 mW |
| Fall Time | 1 ns |
| Operating Temperature (Max) | 150 ℃ |
| Operating Temperature (Min) | -55 ℃ |
| Power Dissipation (Max) | 360 mW |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tape & Reel (TR) |
| Size-Length | 2 mm |
| Size-Width | 1.25 mm |
| Size-Height | 1 mm |
| Operating Temperature | -55℃ ~ 150℃ |
The FDG8850NZ is a dual N-channel logic level enhancement-mode MOSFET with high cell density and DMOS technology. This very high density process is especially tailored to minimize ON-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETs. Since bias resistors are not required, this dual digital FET can replace several different digital transistors, with different bias resistor values.
● Very small package outline
● Very low level gate drive requirements allowing direct operation in 3V circuits (VGS (th) <1.5V)
● ±12V Gate to source voltage
● 0.75A Continuous drain current
● 2.2A Pulsed drain current
Fairchild
5 Pages / 0.31 MByte
Fairchild
8 Pages / 0.4 MByte
Fairchild
4 Pages / 0.17 MByte
Fairchild
1 Pages / 0.14 MByte
Fairchild
Trans MOSFET N-CH 30V 0.75A 6Pin SC-70 T/R
ON Semiconductor
Trans MOSFET N-CH 30V 0.75A 6Pin SC-70 T/R
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